谁有vhdl的数据采集器的程序？

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ADKZ is
port ( d : in std_logic_vector(7 downto 0); --ADC0809输出的采样数据
clk,eoc : in std_logic; --clk为系统时钟，eoc为ADC0809转换结束信号
clk1,start, ale,en: out std_logic; --ADC0809控制信号
q : out std_logic_vector(7 downto 0));
end ADKZ;
architecture behav of ADKZ is
type states is ( st0,st1, st2, st3, st4,st5,st6); --定义各状态的子类型
signal current_state, next_state:states;
signal regl :std_logic_vector(7 downto 0); --中间数据寄存信号
signal qq:std_logic_vector(7 downto 0);
signal clk10k:std_logic;
begin
clock:process(clk) --对系统时钟进行分频，得到ADC0809转换工作时钟
variable cnt:integer range 0 to 4999;
begin
if clk='1'and clk'event then
if cnt=4999 then cnt:=0;
else
if cnt<2500 then clk10k<='1'; --clk1=500khz
else clk10k<='0';
end if;
cnt:=cnt+1;
end if;
end if;
clk1<=clk10k;
if clk10k'event and clk10k='1' then --在clk1的上升沿，转换至下一状态
current_state <=next_state;
end if;
end process;
com:process(current_state,eoc) --规定各种状态的转换方式
begin
case current_state is
when st0=>next_state<=st1;ale<='0';start<='0';en<='0';
when st1=>next_state<=st2;ale<='1';start<='0';en<='0';
when st2=>next_state<=st3;ale<='0';start<='1';en<='0';
when st3=> ale<='0';start<='0';en<='0';
if eoc='1' then next_state<=st3; --检测EOC的下降沿
else next_state<=st4;
end if;
when st4=> ale<='0';start<='0';en<='0';
if eoc='0' then next_state<=st4; --检测EOC的上升沿
else next_state<=st5;
end if;
when st5=>next_state<=st6;ale<='0';start<='0';en<='1';
when st6=>next_state<=st0;ale<='0';start<='0';en<='1';regl<=d;
when others=> next_state<=st0;ale<='0';start<='0';en<='0';
end case;
end process;
q<=regl;
end behav;